Document Type

Conference Proceeding

Publication Date

9-16-2013

Abstract

In any channel operating at 2 Gbps and above, conductor and dielectric losses can dominate channel performance. These effects must be included in any accurate system simulation. The problem isn't that simulators don't do this; there are several choices in interconnect loss mathematical expressions and it's difficult to decide how to transform fab information into simulator input. There are different combinations of parameterized mathematical expressions for dielectric and conductor loss which are in popular use in the industry. Each works to some extent. This paper takes each mathematical expression, explains its origin, evaluates its predicted insertion loss magnitude and phase then explores how the expression scales. This is useful when translating test coupon results into accurate simulation predictions.

Journal Title

DesignCon 2013: Where Chipheads Connect

Volume

1

First Page

469

Last Page

494

ISBN

9781627484725

First Department

Engineering

Acknowledgements

Retrieved February 2, 2021 from https://www.ccnlabs.com/uploads/5/5/1/0/55102705/tn20130130_lossmodels_designcon2013_5-wa4.pdf

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